2017-08-22 14:30:33 +00:00
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/**
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* Marlin 3D Printer Firmware
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* Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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*
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* Based on Sprinter and grbl.
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* Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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2017-08-26 20:25:25 +00:00
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#ifdef TARGET_LPC1768
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2017-10-24 22:28:33 +00:00
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#include "../../inc/MarlinConfig.h"
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2017-08-22 14:30:33 +00:00
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#include "HardwareSerial.h"
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2018-01-15 22:00:59 +00:00
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#if SERIAL_PORT == 0 || SERIAL_PORT_2 == 0
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HardwareSerial Serial = HardwareSerial(LPC_UART0);
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#elif SERIAL_PORT == 1 || SERIAL_PORT_2 == 1
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HardwareSerial Serial1 = HardwareSerial((LPC_UART_TypeDef *) LPC_UART1);
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#elif SERIAL_PORT == 2 || SERIAL_PORT_2 == 2
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HardwareSerial Serial2 = HardwareSerial(LPC_UART2);
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#elif SERIAL_PORT == 3 || SERIAL_PORT_2 == 3
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HardwareSerial Serial3 = HardwareSerial(LPC_UART3);
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#endif
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2017-10-24 22:28:33 +00:00
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void HardwareSerial::begin(uint32_t baudrate) {
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UART_CFG_Type UARTConfigStruct;
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PINSEL_CFG_Type PinCfg;
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UART_FIFO_CFG_Type FIFOConfig;
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if (UARTx == LPC_UART0) {
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2018-01-15 22:00:59 +00:00
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// Initialize UART0 pin connect
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2017-10-24 22:28:33 +00:00
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PinCfg.Funcnum = 1;
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PinCfg.OpenDrain = 0;
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PinCfg.Pinmode = 0;
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PinCfg.Pinnum = 2;
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PinCfg.Portnum = 0;
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PINSEL_ConfigPin(&PinCfg);
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PinCfg.Pinnum = 3;
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PINSEL_ConfigPin(&PinCfg);
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2018-01-15 22:00:59 +00:00
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} else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) {
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// Initialize UART1 pin connect
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2017-10-24 22:28:33 +00:00
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PinCfg.Funcnum = 1;
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PinCfg.OpenDrain = 0;
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PinCfg.Pinmode = 0;
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PinCfg.Pinnum = 15;
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PinCfg.Portnum = 0;
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PINSEL_ConfigPin(&PinCfg);
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PinCfg.Pinnum = 16;
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PINSEL_ConfigPin(&PinCfg);
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2018-01-15 22:00:59 +00:00
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} else if (UARTx == LPC_UART2) {
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// Initialize UART2 pin connect
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2017-10-24 22:28:33 +00:00
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PinCfg.Funcnum = 1;
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PinCfg.OpenDrain = 0;
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PinCfg.Pinmode = 0;
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PinCfg.Pinnum = 10;
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PinCfg.Portnum = 0;
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PINSEL_ConfigPin(&PinCfg);
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PinCfg.Pinnum = 11;
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PINSEL_ConfigPin(&PinCfg);
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2018-01-15 22:00:59 +00:00
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} else if (UARTx == LPC_UART3) {
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// Initialize UART2 pin connect
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2017-10-24 22:28:33 +00:00
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PinCfg.Funcnum = 1;
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PinCfg.OpenDrain = 0;
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PinCfg.Pinmode = 0;
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PinCfg.Pinnum = 0;
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PinCfg.Portnum = 0;
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PINSEL_ConfigPin(&PinCfg);
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PinCfg.Pinnum = 1;
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PINSEL_ConfigPin(&PinCfg);
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2017-09-27 09:57:33 +00:00
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}
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2017-09-28 15:16:25 +00:00
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2018-01-05 16:25:42 +00:00
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/* Initialize UART Configuration parameter structure to default state:
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* Baudrate = 9600bps
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* 8 data bit
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* 1 Stop bit
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* None parity
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*/
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UART_ConfigStructInit(&UARTConfigStruct);
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// Re-configure baudrate
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UARTConfigStruct.Baud_rate = baudrate;
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// Initialize eripheral with given to corresponding parameter
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2017-10-24 22:28:33 +00:00
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UART_Init(UARTx, &UARTConfigStruct);
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2017-10-27 04:33:43 +00:00
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2017-10-24 22:28:33 +00:00
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// Enable and reset the TX and RX FIFOs
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UART_FIFOConfigStructInit(&FIFOConfig);
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UART_FIFOConfig(UARTx, &FIFOConfig);
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2018-01-05 16:25:42 +00:00
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// Enable UART Transmit
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2017-10-24 22:28:33 +00:00
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UART_TxCmd(UARTx, ENABLE);
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// Configure Interrupts
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UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
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UART_IntConfig(UARTx, UART_INTCFG_RLS, ENABLE);
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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if (UARTx == LPC_UART0) NVIC_EnableIRQ(UART0_IRQn);
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else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) NVIC_EnableIRQ(UART1_IRQn);
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else if (UARTx == LPC_UART2) NVIC_EnableIRQ(UART2_IRQn);
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else if (UARTx == LPC_UART3) NVIC_EnableIRQ(UART3_IRQn);
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2017-10-24 22:28:33 +00:00
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RxQueueWritePos = RxQueueReadPos = 0;
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#if TX_BUFFER_SIZE > 0
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TxQueueWritePos = TxQueueReadPos = 0;
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#endif
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2017-09-27 09:57:33 +00:00
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}
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2017-09-28 15:16:25 +00:00
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2017-10-24 22:28:33 +00:00
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int HardwareSerial::peek() {
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int byte = -1;
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2017-08-22 14:30:33 +00:00
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2018-01-15 22:00:59 +00:00
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// Temporarily lock out UART receive interrupts during this read so the UART receive
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// interrupt won't cause problems with the index values
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2017-10-24 22:28:33 +00:00
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UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
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2017-10-27 04:33:43 +00:00
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2017-10-24 22:28:33 +00:00
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if (RxQueueReadPos != RxQueueWritePos)
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byte = RxBuffer[RxQueueReadPos];
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2018-01-15 22:00:59 +00:00
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// Re-enable UART interrupts
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2017-10-24 22:28:33 +00:00
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UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
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2017-10-27 04:33:43 +00:00
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2017-10-24 22:28:33 +00:00
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return byte;
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2017-09-28 15:16:25 +00:00
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}
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2017-10-24 22:28:33 +00:00
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int HardwareSerial::read() {
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int byte = -1;
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2018-01-15 22:00:59 +00:00
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// Temporarily lock out UART receive interrupts during this read so the UART receive
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// interrupt won't cause problems with the index values
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2017-10-24 22:28:33 +00:00
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UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
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2017-10-27 04:33:43 +00:00
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2017-10-24 22:28:33 +00:00
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if (RxQueueReadPos != RxQueueWritePos) {
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byte = RxBuffer[RxQueueReadPos];
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RxQueueReadPos = (RxQueueReadPos + 1) % RX_BUFFER_SIZE;
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2017-08-22 14:30:33 +00:00
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}
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2017-09-28 15:16:25 +00:00
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2018-01-15 22:00:59 +00:00
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// Re-enable UART interrupts
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2017-10-24 22:28:33 +00:00
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UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
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2017-10-27 04:33:43 +00:00
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2017-10-24 22:28:33 +00:00
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return byte;
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}
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size_t HardwareSerial::write(uint8_t send) {
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2018-01-15 22:00:59 +00:00
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#if TX_BUFFER_SIZE > 0
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size_t bytes = 0;
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uint32_t fifolvl = 0;
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2017-10-24 22:28:33 +00:00
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2018-01-15 22:00:59 +00:00
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// If the Tx Buffer is full, wait for space to clear
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if ((TxQueueWritePos+1) % TX_BUFFER_SIZE == TxQueueReadPos) flushTX();
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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// Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't
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// cause problems with the index values
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UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
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2017-10-24 22:28:33 +00:00
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2018-01-15 22:00:59 +00:00
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// LPC17xx.h incorrectly defines FIFOLVL as a uint8_t, when it's actually a 32-bit register
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if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) {
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fifolvl = *(reinterpret_cast<volatile uint32_t *>(&((LPC_UART1_TypeDef *) UARTx)->FIFOLVL));
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} else fifolvl = *(reinterpret_cast<volatile uint32_t *>(&UARTx->FIFOLVL));
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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// If the queue is empty and there's space in the FIFO, immediately send the byte
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if (TxQueueWritePos == TxQueueReadPos && fifolvl < UART_TX_FIFO_SIZE) {
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bytes = UART_Send(UARTx, &send, 1, BLOCKING);
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}
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// Otherwiise, write the byte to the transmit buffer
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else if ((TxQueueWritePos+1) % TX_BUFFER_SIZE != TxQueueReadPos) {
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TxBuffer[TxQueueWritePos] = send;
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TxQueueWritePos = (TxQueueWritePos+1) % TX_BUFFER_SIZE;
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bytes++;
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}
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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// Re-enable the TX Interrupt
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UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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return bytes;
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#else
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return UART_Send(UARTx, &send, 1, BLOCKING);
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#endif
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2017-10-24 22:28:33 +00:00
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}
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2017-09-28 15:16:25 +00:00
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2017-10-24 22:28:33 +00:00
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#if TX_BUFFER_SIZE > 0
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void HardwareSerial::flushTX() {
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2018-01-15 22:00:59 +00:00
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// Wait for the tx buffer and FIFO to drain
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2017-10-24 22:28:33 +00:00
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while (TxQueueWritePos != TxQueueReadPos && UART_CheckBusy(UARTx) == SET);
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}
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2017-09-28 15:16:25 +00:00
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#endif
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2017-10-24 22:28:33 +00:00
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int HardwareSerial::available() {
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return (RxQueueWritePos + RX_BUFFER_SIZE - RxQueueReadPos) % RX_BUFFER_SIZE;
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}
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void HardwareSerial::flush() {
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RxQueueWritePos = 0;
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RxQueueReadPos = 0;
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}
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void HardwareSerial::printf(const char *format, ...) {
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char RxBuffer[256];
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va_list vArgs;
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va_start(vArgs, format);
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int length = vsnprintf(RxBuffer, 256, format, vArgs);
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va_end(vArgs);
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if (length > 0 && length < 256) {
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for (int i = 0; i < length; ++i)
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write(RxBuffer[i]);
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}
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}
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void HardwareSerial::IRQHandler() {
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uint32_t IIRValue;
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uint8_t LSRValue, byte;
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2017-09-28 15:16:25 +00:00
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2017-10-24 22:28:33 +00:00
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IIRValue = UART_GetIntId(UARTx);
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2018-01-15 22:00:59 +00:00
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IIRValue &= UART_IIR_INTID_MASK; // check bit 1~3, interrupt identification
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2017-09-28 15:16:25 +00:00
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2018-01-15 22:00:59 +00:00
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// Receive Line Status
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if (IIRValue == UART_IIR_INTID_RLS) {
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2017-10-24 22:28:33 +00:00
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LSRValue = UART_GetLineStatus(UARTx);
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2018-01-15 22:00:59 +00:00
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// Receive Line Status
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if (LSRValue & (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_RXFE | UART_LSR_BI)) {
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// There are errors or break interrupt
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// Read LSR will clear the interrupt
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2017-10-24 22:28:33 +00:00
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Status = LSRValue;
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2018-01-15 22:00:59 +00:00
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byte = UART_ReceiveByte(UARTx); // Dummy read on RX to clear interrupt, then bail out
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2017-09-30 21:06:43 +00:00
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return;
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}
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2017-10-24 22:28:33 +00:00
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}
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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// Receive Data Available
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if (IIRValue == UART_IIR_INTID_RDA) {
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// Clear the FIFO
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while (UART_Receive(UARTx, &byte, 1, NONE_BLOCKING)) {
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if ((RxQueueWritePos + 1) % RX_BUFFER_SIZE != RxQueueReadPos) {
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2017-10-24 22:28:33 +00:00
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RxBuffer[RxQueueWritePos] = byte;
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2018-01-15 22:00:59 +00:00
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RxQueueWritePos = (RxQueueWritePos + 1) % RX_BUFFER_SIZE;
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} else
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2017-10-24 22:28:33 +00:00
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break;
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2017-09-30 21:06:43 +00:00
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}
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2018-01-15 22:00:59 +00:00
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// Character timeout indicator
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} else if (IIRValue == UART_IIR_INTID_CTI) {
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// Character Time-out indicator
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Status |= 0x100; // Bit 9 as the CTI error
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2017-08-22 14:30:33 +00:00
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}
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2017-10-24 22:28:33 +00:00
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#if TX_BUFFER_SIZE > 0
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if (IIRValue == UART_IIR_INTID_THRE) {
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2018-01-15 22:00:59 +00:00
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// Disable THRE interrupt
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2017-10-24 22:28:33 +00:00
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UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
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2018-01-15 22:00:59 +00:00
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// Wait for FIFO buffer empty
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2017-10-24 22:28:33 +00:00
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while (UART_CheckBusy(UARTx) == SET);
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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// Transfer up to UART_TX_FIFO_SIZE bytes of data
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2017-10-24 22:28:33 +00:00
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for (int i = 0; i < UART_TX_FIFO_SIZE && TxQueueWritePos != TxQueueReadPos; i++) {
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2018-01-15 22:00:59 +00:00
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// Move a piece of data into the transmit FIFO
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if (UART_Send(UARTx, &TxBuffer[TxQueueReadPos], 1, NONE_BLOCKING)) {
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2017-10-24 22:28:33 +00:00
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TxQueueReadPos = (TxQueueReadPos+1) % TX_BUFFER_SIZE;
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2018-01-15 22:00:59 +00:00
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} else break;
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2017-10-24 22:28:33 +00:00
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}
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2017-10-27 04:33:43 +00:00
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2018-01-15 22:00:59 +00:00
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// If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled
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if (TxQueueWritePos == TxQueueReadPos) {
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2017-10-24 22:28:33 +00:00
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UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
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2018-01-15 22:00:59 +00:00
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} else UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
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2017-09-30 21:06:43 +00:00
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}
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2017-10-24 22:28:33 +00:00
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#endif
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}
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#ifdef __cplusplus
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extern "C" {
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#endif
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2018-01-15 22:00:59 +00:00
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void UART0_IRQHandler(void) {
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#if SERIAL_PORT == 0 || SERIAL_PORT_2 == 0
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Serial.IRQHandler();
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#endif
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2017-08-22 14:30:33 +00:00
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}
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2018-01-15 22:00:59 +00:00
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void UART1_IRQHandler(void) {
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#if SERIAL_PORT == 1 || SERIAL_PORT_2 == 1
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Serial1.IRQHandler();
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#endif
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2017-08-22 14:30:33 +00:00
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}
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2017-10-24 22:28:33 +00:00
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2018-01-15 22:00:59 +00:00
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void UART2_IRQHandler(void) {
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#if SERIAL_PORT == 2 || SERIAL_PORT_2 == 2
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Serial2.IRQHandler();
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#endif
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2017-08-22 14:30:33 +00:00
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}
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2017-10-24 22:28:33 +00:00
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2018-01-15 22:00:59 +00:00
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void UART3_IRQHandler(void) {
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#if SERIAL_PORT == 3 || SERIAL_PORT_2 == 3
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Serial3.IRQHandler();
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#endif
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2017-09-28 15:16:25 +00:00
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}
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2017-08-22 14:30:33 +00:00
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#ifdef __cplusplus
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2017-09-28 15:16:25 +00:00
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}
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2017-08-22 14:30:33 +00:00
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#endif
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2017-08-26 20:25:25 +00:00
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#endif // TARGET_LPC1768
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