mirror of
https://github.com/MarlinFirmware/Marlin.git
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📝 KHz => kHz (#23512)
This commit is contained in:
Keith Bennett
GitHub
parent
9086082c1f
commit
3e2a38b653
30 changed files with 52 additions and 52 deletions
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@ -561,7 +561,7 @@
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* FAST_PWM_FAN_FREQUENCY
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* Set this to your desired frequency.
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* For AVR, if left undefined this defaults to F = F_CPU/(2*255*1)
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* i.e., F = 31.4KHz on 16MHz microcontrollers or F = 39.2KHz on 20MHz microcontrollers.
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* i.e., F = 31.4kHz on 16MHz microcontrollers or F = 39.2kHz on 20MHz microcontrollers.
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* For non AVR, if left undefined this defaults to F = 1Khz.
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* This F value is only to protect the hardware from an absence of configuration
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* and not to complete it when users are not aware that the frequency must be specifically set to support the target board.
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@ -571,8 +571,8 @@
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*
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* USE_OCR2A_AS_TOP [undefined by default]
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* Boards that use TIMER2 for PWM have limitations resulting in only a few possible frequencies on TIMER2:
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* 16MHz MCUs: [62.5KHz, 31.4KHz (default), 7.8KHz, 3.92KHz, 1.95KHz, 977Hz, 488Hz, 244Hz, 60Hz, 122Hz, 30Hz]
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* 20MHz MCUs: [78.1KHz, 39.2KHz (default), 9.77KHz, 4.9KHz, 2.44KHz, 1.22KHz, 610Hz, 305Hz, 153Hz, 76Hz, 38Hz]
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* 16MHz MCUs: [62.5kHz, 31.4kHz (default), 7.8kHz, 3.92kHz, 1.95kHz, 977Hz, 488Hz, 244Hz, 60Hz, 122Hz, 30Hz]
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* 20MHz MCUs: [78.1kHz, 39.2kHz (default), 9.77kHz, 4.9kHz, 2.44kHz, 1.22kHz, 610Hz, 305Hz, 153Hz, 76Hz, 38Hz]
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* A greater range can be achieved by enabling USE_OCR2A_AS_TOP. But note that this option blocks the use of
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* PWM on pin OC2A. Only use this option if you don't need PWM on 0C2A. (Check your schematic.)
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* USE_OCR2A_AS_TOP sacrifices duty cycle control resolution to achieve this broader range of frequencies.
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@ -1179,7 +1179,7 @@
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/**
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* Adaptive Step Smoothing increases the resolution of multi-axis moves, particularly at step frequencies
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* below 1KHz (for AVR) or 10KHz (for ARM), where aliasing between axes in multi-axis moves causes audible
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* below 1kHz (for AVR) or 10kHz (for ARM), where aliasing between axes in multi-axis moves causes audible
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* vibration and surface artifacts. The algorithm adapts to provide the best possible step smoothing at the
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* lowest stepping frequencies.
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*/
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@ -3419,14 +3419,14 @@
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/**
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* PHOTO_PULSES_US may need adjustment depending on board and camera model.
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* Pin must be running at 48.4KHz.
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* Pin must be running at 48.4kHz.
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* Be sure to use a PHOTOGRAPH_PIN which can rise and fall quick enough.
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* (e.g., MKS SBase temp sensor pin was too slow, so used P1.23 on J8.)
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*
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* Example pulse data for Nikon: https://bit.ly/2FKD0Aq
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* IR Wiring: https://git.io/JvJf7
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*/
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//#define PHOTO_PULSES_US { 2000, 27850, 400, 1580, 400, 3580, 400 } // (µs) Durations for each 48.4KHz oscillation
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//#define PHOTO_PULSES_US { 2000, 27850, 400, 1580, 400, 3580, 400 } // (µs) Durations for each 48.4kHz oscillation
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#ifdef PHOTO_PULSES_US
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#define PHOTO_PULSE_DELAY_US 13 // (µs) Approximate duration of each HIGH and LOW pulse in the oscillation
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#endif
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@ -245,7 +245,7 @@ uint16_t set_pwm_frequency_hz(const_float_t hz, const float dca, const float dcb
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float count = 0;
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if (hz > 0 && (dca || dcb || dcc)) {
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count = float(F_CPU) / hz; // 1x prescaler, TOP for 16MHz base freq.
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uint16_t prescaler; // Range of 30.5Hz (65535) 64.5KHz (>31)
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uint16_t prescaler; // Range of 30.5Hz (65535) 64.5kHz (>31)
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if (count >= 255. * 256.) { prescaler = 1024; SET_CS(5, PRESCALER_1024); }
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else if (count >= 255. * 64.) { prescaler = 256; SET_CS(5, PRESCALER_256); }
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@ -277,7 +277,7 @@ uint16_t set_pwm_frequency_hz(const_float_t hz, const float dca, const float dcb
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// Restore the default for Timer 5
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SET_WGM(5, PWM_PC_8); // PWM 8-bit (Phase Correct)
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SET_COMS(5, NORMAL, NORMAL, NORMAL); // Do nothing
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SET_CS(5, PRESCALER_64); // 16MHz / 64 = 250KHz
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SET_CS(5, PRESCALER_64); // 16MHz / 64 = 250kHz
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OCR5A = OCR5B = OCR5C = 0;
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}
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return round(count);
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@ -491,9 +491,9 @@
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* 1 : 4 - 5 MHz
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* 2 : 2 - 2.5 MHz
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* 3 : 1 - 1.25 MHz
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* 4 : 500 - 625 KHz
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* 5 : 250 - 312 KHz
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* 6 : 125 - 156 KHz
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* 4 : 500 - 625 kHz
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* 5 : 250 - 312 kHz
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* 6 : 125 - 156 kHz
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*/
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void spiInit(uint8_t spiRate) {
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switch (spiRate) {
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@ -25,7 +25,7 @@
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* is NOT used to directly toggle pins. The ISR writes to the pin assigned to
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* that interrupt.
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*
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* All PWMs use the same repetition rate. The G2 needs about 10KHz min in order to
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* All PWMs use the same repetition rate. The G2 needs about 10kHz min in order to
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* not have obvious ripple on the Vref signals.
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*
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* The data structures are setup to minimize the computation done by the ISR which
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@ -53,7 +53,7 @@
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* The net result is that both the g_pinStatus[pin] array and the PIO_OSR register
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* needs to be looked at when determining if a pin is an input or an output.
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*
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* b) Due has only pins 6, 7, 8 & 9 enabled for PWMs. FYI - they run at 1KHz
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* b) Due has only pins 6, 7, 8 & 9 enabled for PWMs. FYI - they run at 1kHz
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*
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* c) NUM_DIGITAL_PINS does not include the analog pins
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*
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@ -62,7 +62,7 @@ const tTimerConfig timer_config[NUM_HARDWARE_TIMERS] = {
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Timer_clock1: Prescaler 2 -> 42MHz
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Timer_clock2: Prescaler 8 -> 10.5MHz
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Timer_clock3: Prescaler 32 -> 2.625MHz
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Timer_clock4: Prescaler 128 -> 656.25KHz
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Timer_clock4: Prescaler 128 -> 656.25kHz
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*/
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void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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@ -74,9 +74,9 @@ extern "C" {
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//@{
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enum genclk_source {
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32KHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32KHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32KHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_RC = 0, //!< Internal 32kHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_XTAL = 1, //!< External 32kHz crystal oscillator as PCK source clock
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GENCLK_PCK_SRC_SLCK_BYPASS = 2, //!< External 32kHz bypass oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_4M_RC = 3, //!< Internal 4MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_8M_RC = 4, //!< Internal 8MHz RC oscillator as PCK source clock
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GENCLK_PCK_SRC_MAINCK_12M_RC = 5, //!< Internal 12MHz RC oscillator as PCK source clock
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@ -93,9 +93,9 @@ extern "C" {
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//! \name Oscillator identifiers
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//@{
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#define OSC_SLCK_32K_RC 0 //!< Internal 32KHz RC oscillator.
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#define OSC_SLCK_32K_XTAL 1 //!< External 32KHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS 2 //!< External 32KHz bypass oscillator.
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#define OSC_SLCK_32K_RC 0 //!< Internal 32kHz RC oscillator.
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#define OSC_SLCK_32K_XTAL 1 //!< External 32kHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS 2 //!< External 32kHz bypass oscillator.
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#define OSC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator.
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#define OSC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator.
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#define OSC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator.
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@ -105,9 +105,9 @@ extern "C" {
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//! \name Oscillator clock speed in hertz
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//@{
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#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32KHz RC oscillator.
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#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32KHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32KHz bypass oscillator.
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#define OSC_SLCK_32K_RC_HZ CHIP_FREQ_SLCK_RC //!< Internal 32kHz RC oscillator.
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#define OSC_SLCK_32K_XTAL_HZ BOARD_FREQ_SLCK_XTAL //!< External 32kHz crystal oscillator.
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#define OSC_SLCK_32K_BYPASS_HZ BOARD_FREQ_SLCK_BYPASS //!< External 32kHz bypass oscillator.
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#define OSC_MAINCK_4M_RC_HZ CHIP_FREQ_MAINCK_RC_4MHZ //!< Internal 4MHz RC oscillator.
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#define OSC_MAINCK_8M_RC_HZ CHIP_FREQ_MAINCK_RC_8MHZ //!< Internal 8MHz RC oscillator.
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#define OSC_MAINCK_12M_RC_HZ CHIP_FREQ_MAINCK_RC_12MHZ //!< Internal 12MHz RC oscillator.
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@ -156,9 +156,9 @@ extern "C" {
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//! \name Master Clock Sources (MCK)
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//@{
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#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32KHz RC oscillator as master source clock
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#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32KHz crystal oscillator as master source clock
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#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32KHz bypass oscillator as master source clock
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#define SYSCLK_SRC_SLCK_RC 0 //!< Internal 32kHz RC oscillator as master source clock
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#define SYSCLK_SRC_SLCK_XTAL 1 //!< External 32kHz crystal oscillator as master source clock
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#define SYSCLK_SRC_SLCK_BYPASS 2 //!< External 32kHz bypass oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_4M_RC 3 //!< Internal 4MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_8M_RC 4 //!< Internal 8MHz RC oscillator as master source clock
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#define SYSCLK_SRC_MAINCK_12M_RC 5 //!< Internal 12MHz RC oscillator as master source clock
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@ -39,7 +39,7 @@ void watchdogSetup() {
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uint32_t timeout = TERN(WATCHDOG_DURATION_8S, 8000, 4000);
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// Calculate timeout value in WDT counter ticks: This assumes
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// the slow clock is running at 32.768 KHz watchdog
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// the slow clock is running at 32.768 kHz watchdog
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// frequency is therefore 32768 / 128 = 256 Hz
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timeout = (timeout << 8) / 1000;
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if (timeout == 0)
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@ -176,7 +176,7 @@ int i2s_init() {
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*
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* fwclk = fbclk / 32
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*
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* for fwclk = 250KHz (4µS pulse time)
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* for fwclk = 250kHz (4µS pulse time)
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* N = 10
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* M = 20
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*/
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@ -26,7 +26,7 @@
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* These are based on the LPC1768 pinMode, digitalRead & digitalWrite routines.
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*
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* Couldn't just call exact copies because the overhead killed the LCD update speed
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* With an intermediate level the softspi was running in the 10-20KHz range which
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* With an intermediate level the softspi was running in the 10-20kHz range which
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* resulted in using about about 25% of the CPU's time.
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*/
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@ -27,7 +27,7 @@
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* These are based on the LPC1768 pinMode, digitalRead & digitalWrite routines.
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*
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* Couldn't just call exact copies because the overhead killed the LCD update speed
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* With an intermediate level the softspi was running in the 10-20KHz range which
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* With an intermediate level the softspi was running in the 10-20kHz range which
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* resulted in using about about 25% of the CPU's time.
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*/
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@ -26,7 +26,7 @@
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* These are based on the LPC1768 pinMode, digitalRead & digitalWrite routines.
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*
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* Couldn't just call exact copies because the overhead killed the LCD update speed
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* With an intermediate level the softspi was running in the 10-20KHz range which
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* With an intermediate level the softspi was running in the 10-20kHz range which
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* resulted in using about about 25% of the CPU's time.
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*/
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@ -27,7 +27,7 @@
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* These are based on the LPC1768 pinMode, digitalRead & digitalWrite routines.
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*
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* Couldn't just call exact copies because the overhead killed the LCD update speed
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* With an intermediate level the softspi was running in the 10-20KHz range which
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* With an intermediate level the softspi was running in the 10-20kHz range which
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* resulted in using about about 25% of the CPU's time.
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*/
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@ -79,7 +79,7 @@ void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
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rtc->MODE0.INTENCLR.reg = RTC_MODE0_INTENCLR_CMP0;
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// RTC clock setup
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K; // External 32.768KHz oscillator
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OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K; // External 32.768kHz oscillator
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// Stop timer, just in case, to be able to reconfigure it
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rtc->MODE0.CTRLA.bit.ENABLE = false;
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@ -59,7 +59,7 @@ DMA_HandleTypeDef hdma_sdio;
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/*
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SDIO_INIT_CLK_DIV is 118
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SDIO clock frequency is 48MHz / (TRANSFER_CLOCK_DIV + 2)
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SDIO init clock frequency should not exceed 400KHz = 48MHz / (118 + 2)
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SDIO init clock frequency should not exceed 400kHz = 48MHz / (118 + 2)
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Default TRANSFER_CLOCK_DIV is 2 (118 / 40)
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Default SDIO clock frequency is 48MHz / (2 + 2) = 12 MHz
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@ -48,7 +48,7 @@
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#define TIMER_INDEX_(T) TIMER##T##_INDEX // TIMER#_INDEX enums (timer_index_t) depend on TIM#_BASE defines.
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#define TIMER_INDEX(T) TIMER_INDEX_(T) // Convert Timer ID to HardwareTimer_Handle index.
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#define TEMP_TIMER_FREQUENCY 1000 // Temperature::isr() is expected to be called at around 1KHz
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#define TEMP_TIMER_FREQUENCY 1000 // Temperature::isr() is expected to be called at around 1kHz
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// TODO: get rid of manual rate/prescale/ticks/cycles taken for procedures in stepper.cpp
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#define STEPPER_TIMER_RATE 2000000 // 2 Mhz
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* Timer_clock1: Prescaler 2 -> 36 MHz
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* Timer_clock2: Prescaler 8 -> 9 MHz
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* Timer_clock3: Prescaler 32 -> 2.25 MHz
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* Timer_clock4: Prescaler 128 -> 562.5 KHz
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* Timer_clock4: Prescaler 128 -> 562.5 kHz
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*/
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/**
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@ -41,7 +41,7 @@ typedef uint32_t hal_timer_t;
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#define FTM0_TIMER_PRESCALE_BITS 0b011
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#define FTM1_TIMER_PRESCALE_BITS 0b010
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#define FTM0_TIMER_RATE (F_BUS / (FTM0_TIMER_PRESCALE)) // 60MHz / 8 = 7500KHz
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#define FTM0_TIMER_RATE (F_BUS / (FTM0_TIMER_PRESCALE)) // 60MHz / 8 = 7500kHz
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#define FTM1_TIMER_RATE (F_BUS / (FTM1_TIMER_PRESCALE)) // 60MHz / 4 = 15MHz
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#define HAL_TIMER_RATE (FTM0_TIMER_RATE)
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#define FTM0_TIMER_PRESCALE_BITS 0b011
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#define FTM1_TIMER_PRESCALE_BITS 0b010
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#define FTM0_TIMER_RATE (F_BUS / FTM0_TIMER_PRESCALE) // 60MHz / 8 = 7500KHz
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#define FTM0_TIMER_RATE (F_BUS / FTM0_TIMER_PRESCALE) // 60MHz / 8 = 7500kHz
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#define FTM1_TIMER_RATE (F_BUS / FTM1_TIMER_PRESCALE) // 60MHz / 4 = 15MHz
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#define HAL_TIMER_RATE (FTM0_TIMER_RATE)
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@ -38,9 +38,9 @@
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* 1 : 4 - 5 MHz
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* 2 : 2 - 2.5 MHz
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* 3 : 1 - 1.25 MHz
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* 4 : 500 - 625 KHz
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* 5 : 250 - 312 KHz
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* 6 : 125 - 156 KHz
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* 4 : 500 - 625 kHz
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* 5 : 250 - 312 kHz
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* 6 : 125 - 156 kHz
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*
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* On AVR, actual speed is F_CPU/2^(1 + index).
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* On other platforms, speed should be in range given above where possible.
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@ -82,7 +82,7 @@ void DigipotI2C::set_current(const uint8_t channel, const float current) {
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void DigipotI2C::init() {
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#if MB(MKS_SBASE)
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configure_i2c(16); // Set clock_option to 16 ensure I2C is initialized at 400KHz
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configure_i2c(16); // Set clock_option to 16 ensure I2C is initialized at 400kHz
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#else
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Wire.begin();
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#endif
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@ -53,7 +53,7 @@
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// b7 b6 b5 b4 ~b4 ... hi bits, NOT last bit
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// b3 b2 b1 b0 ~b0 ... lo bits, NOT last bit
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//
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void M672_send(uint8_t b) { // bit rate requirement: 1KHz +/- 30%
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void M672_send(uint8_t b) { // bit rate requirement: 1kHz +/- 30%
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LOOP_L_N(bits, 14) {
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switch (bits) {
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default: { OUT_WRITE(SMART_EFFECTOR_MOD_PIN, !!(b & 0x80)); b <<= 1; break; } // send bit, shift next into place
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@ -43,7 +43,7 @@
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*
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* If no PWM pin is defined then M3/M4 just turns it on.
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*
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* At least 12.8KHz (50Hz * 256) is needed for Spindle PWM.
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* At least 12.8kHz (50Hz * 256) is needed for Spindle PWM.
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* Hardware PWM is required on AVR. ISRs are too slow.
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*
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* NOTE: WGM for timers 3, 4, and 5 must be either Mode 1 or Mode 5.
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@ -352,7 +352,7 @@ void Endstops::init() {
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} // Endstops::init
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// Called at ~1KHz from Temperature ISR: Poll endstop state if required
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||||
// Called at ~1kHz from Temperature ISR: Poll endstop state if required
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void Endstops::poll() {
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||||
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||||
TERN_(PINS_DEBUGGING, run_monitor()); // Report changes in endstop status
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||||
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|
@ -403,7 +403,7 @@ void Endstops::not_homing() {
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void Endstops::resync() {
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if (!abort_enabled()) return; // If endstops/probes are disabled the loop below can hang
|
||||
|
||||
// Wait for Temperature ISR to run at least once (runs at 1KHz)
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||||
// Wait for Temperature ISR to run at least once (runs at 1kHz)
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||||
TERN(ENDSTOP_INTERRUPTS_FEATURE, update(), safe_delay(2));
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||||
while (TERN0(ENDSTOP_NOISE_THRESHOLD, endstop_poll_count)) safe_delay(1);
|
||||
}
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||||
|
|
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|||
|
|
@ -2495,7 +2495,7 @@ bool Planner::_populate_block(block_t * const block, bool split_move,
|
|||
if (extruder_advance_K[active_extruder] * block->e_D_ratio * block->acceleration * 2 < SQRT(block->nominal_speed_sqr) * block->e_D_ratio)
|
||||
SERIAL_ECHOLNPGM("More than 2 steps per eISR loop executed.");
|
||||
if (block->advance_speed < 200)
|
||||
SERIAL_ECHOLNPGM("eISR running at > 10KHz.");
|
||||
SERIAL_ECHOLNPGM("eISR running at > 10kHz.");
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -883,7 +883,7 @@ class Planner {
|
|||
static void finish_and_disable();
|
||||
|
||||
// Periodic handler to manage the cleaning buffer counter
|
||||
// Called from the Temperature ISR at ~1KHz
|
||||
// Called from the Temperature ISR at ~1kHz
|
||||
static void isr() { if (cleaning_buffer_counter) --cleaning_buffer_counter; }
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -3046,8 +3046,8 @@ public:
|
|||
};
|
||||
|
||||
/**
|
||||
* Handle various ~1KHz tasks associated with temperature
|
||||
* - Heater PWM (~1KHz with scaler)
|
||||
* Handle various ~1kHz tasks associated with temperature
|
||||
* - Heater PWM (~1kHz with scaler)
|
||||
* - LCD Button polling (~500Hz)
|
||||
* - Start / Read one ADC sensor
|
||||
* - Advance Babysteps
|
||||
|
|
@ -3549,7 +3549,7 @@ void Temperature::isr() {
|
|||
adc_sensor_state = next_sensor_state;
|
||||
|
||||
//
|
||||
// Additional ~1KHz Tasks
|
||||
// Additional ~1kHz Tasks
|
||||
//
|
||||
|
||||
#if ENABLED(BABYSTEPPING) && DISABLED(INTEGRATED_BABYSTEPPING)
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#ifndef LSE_STARTUP_TIMEOUT
|
||||
#define LSE_STARTUP_TIMEOUT 50U // No 32.7KHz LSE on this board, reduced to avoid delays
|
||||
#define LSE_STARTUP_TIMEOUT 50U // No 32.7kHz LSE on this board, reduced to avoid delays
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
|
|
|
|||
Loading…
Reference in a new issue