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🐛 Fix AVR maths used by Stepper (#25338)
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@ -27,13 +27,14 @@
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// intRes = longIn1 * longIn2 >> 24
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// uses:
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// A[tmp] to store 0
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// B[tmp] to store bits 16-23 of the 48bit result. The top bit is used to round the two byte result.
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// note that the lower two bytes and the upper byte of the 48bit result are not calculated.
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// this can cause the result to be out by one as the lower bytes may cause carries into the upper ones.
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// B A are bits 24-39 and are the returned value
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// C B A is longIn1
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// D C B A is longIn2
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// r1, r0 for the result of mul.
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// [tmp1] to store 0.
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// [tmp2] to store bits 16-23 of the 56 bit result. The top bit of [tmp2] is used for rounding.
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// Note that the lower two bytes and the upper two bytes of the 56 bit result are not calculated.
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// This can cause the result to be out by one as the lower bytes may cause carries into the upper ones.
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// [intRes] (A B) is bits 24-39 and is the returned value.
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// [longIn1] (C B A) is a 24 bit parameter.
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// [longIn2] (D C B A) is a 32 bit parameter.
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//
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FORCE_INLINE static uint16_t MultiU24X32toH16(uint32_t longIn1, uint32_t longIn2) {
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uint8_t tmp1;
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@ -66,11 +67,9 @@ FORCE_INLINE static uint16_t MultiU24X32toH16(uint32_t longIn1, uint32_t longIn2
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A("add %[tmp2], r1")
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A("adc %A[intRes], %[tmp1]")
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A("adc %B[intRes], %[tmp1]")
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A("lsr %[tmp2]")
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A("adc %A[intRes], %[tmp1]")
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A("adc %B[intRes], %[tmp1]")
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A("mul %D[longIn2], %A[longIn1]")
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A("add %A[intRes], r0")
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A("lsl %[tmp2]")
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A("adc %A[intRes], r0")
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A("adc %B[intRes], r1")
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A("mul %D[longIn2], %B[longIn1]")
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A("add %B[intRes], r0")
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@ -85,11 +84,16 @@ FORCE_INLINE static uint16_t MultiU24X32toH16(uint32_t longIn1, uint32_t longIn2
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return intRes;
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}
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// intRes = intIn1 * intIn2 >> 16
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// intRes = intIn1 * intIn2 >> 8
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// uses:
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// r26 to store 0
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// r27 to store the byte 1 of the 24 bit result
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FORCE_INLINE static uint16_t MultiU16X8toH16(uint8_t charIn1, uint16_t intIn2) {
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// r1, r0 for the result of mul. After the second mul, r0 holds bits 0-7 of the 24 bit result and
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// the top bit of r0 is used for rounding.
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// [tmp] to store 0.
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// [intRes] (A B) is bits 8-15 and is the returned value.
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// [charIn1] is an 8 bit parameter.
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// [intIn2] (B A) is a 16 bit parameter.
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//
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FORCE_INLINE static uint16_t MultiU8X16toH16(uint8_t charIn1, uint16_t intIn2) {
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uint8_t tmp;
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uint16_t intRes;
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__asm__ __volatile__ (
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@ -97,10 +101,8 @@ FORCE_INLINE static uint16_t MultiU16X8toH16(uint8_t charIn1, uint16_t intIn2) {
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A("mul %[charIn1], %B[intIn2]")
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A("movw %A[intRes], r0")
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A("mul %[charIn1], %A[intIn2]")
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A("add %A[intRes], r1")
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A("adc %B[intRes], %[tmp]")
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A("lsr r0")
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A("adc %A[intRes], %[tmp]")
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A("lsl r0")
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A("adc %A[intRes], r1")
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A("adc %B[intRes], %[tmp]")
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A("clr r1")
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: [intRes] "=&r" (intRes),
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@ -2062,7 +2062,7 @@ uint32_t Stepper::calc_timer_interval(uint32_t step_rate) {
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const uint8_t rate_mod_256 = (step_rate & 0x00FF);
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const uintptr_t table_address = uintptr_t(&speed_lookuptable_fast[uint8_t(step_rate >> 8)][0]),
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gain = uint16_t(pgm_read_word(table_address + 2));
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return uint16_t(pgm_read_word(table_address)) - MultiU16X8toH16(rate_mod_256, gain);
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return uint16_t(pgm_read_word(table_address)) - MultiU8X16toH16(rate_mod_256, gain);
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}
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else { // lower step rates
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uintptr_t table_address = uintptr_t(&speed_lookuptable_slow[0][0]);
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@ -114,11 +114,11 @@
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#define TIMER_READ_ADD_AND_STORE_CYCLES 13UL
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// The base ISR
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#define ISR_BASE_CYCLES 1000UL
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#define ISR_BASE_CYCLES 996UL
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// Linear advance base time is 32 cycles
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#if ENABLED(LIN_ADVANCE)
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#define ISR_LA_BASE_CYCLES 32UL
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#define ISR_LA_BASE_CYCLES 30UL
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#else
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#define ISR_LA_BASE_CYCLES 0UL
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#endif
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