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🐛 Fix HC32 watchdog timeout ()

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by reducing PCLK3 clock
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Chris 2024-05-15 22:45:52 +02:00 • committed by GitHub
parent 3dc437add4
commit 6b5e19cfc4
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1 changed files with 1 additions and 1 deletions

2
Marlin/src/HAL/HC32/sysclock.cpp
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@ -104,7 +104,7 @@ void core_hook_sysclock_init() {
.enPclk0Div = ClkSysclkDiv1, // PCLK0 = 200 MHz (Timer6 (not used))
.enPclk1Div = ClkSysclkDiv4, // PCLK1 = 50 MHz (USART, SPI, I2S, Timer0 (step+temp), TimerA (Servo))
.enPclk2Div = ClkSysclkDiv4, // PCLK2 = 50 MHz (ADC)
.enPclk3Div = ClkSysclkDiv4, // PCLK3 = 50 MHz (I2C, WDT)
.enPclk3Div = ClkSysclkDiv8, // PCLK3 = 25 MHz (I2C, WDT)
.enPclk4Div = ClkSysclkDiv2, // PCLK4 = 100 MHz (ADC ctl)
};
sysclock_set_clock_dividers(&sysClkConf);