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🩹Free debug pins in HC32 HAL (#26985)
implements DISABLE_DEBUG and DISABLE_JTAG in HAL
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@ -148,6 +148,25 @@
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#define GET_PIN_MAP_INDEX(pin) pin
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#define GET_PIN_MAP_INDEX(pin) pin
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#define PARSED_PIN_INDEX(code, dval) parser.intval(code, dval)
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#define PARSED_PIN_INDEX(code, dval) parser.intval(code, dval)
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//
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// Debug port disable
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// JTMS / SWDIO = PA13
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// JTCK / SWCLK = PA14
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// JTDI = PA15
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// JTDO = PB3
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// NJTRST = PB4
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//
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#define DBG_SWCLK _BV(0)
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#define DBG_SWDIO _BV(1)
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#define DBG_TDO _BV(2)
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#define DBG_TDI _BV(3)
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#define DBG_TRST _BV(4)
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#define DBG_ALL (DBG_SWCLK | DBG_SWDIO | DBG_TDO | DBG_TDI | DBG_TRST)
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#define JTAGSWD_RESET() PORT_DebugPortSetting(DBG_ALL, Enable);
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#define JTAG_DISABLE() PORT_DebugPortSetting(DBG_TDO | DBG_TDI | DBG_TRST, Disable);
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#define JTAGSWD_DISABLE() PORT_DebugPortSetting(DBG_ALL, Disable);
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//
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//
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// MarlinHAL implementation
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// MarlinHAL implementation
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//
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//
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@ -45,10 +45,13 @@
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#endif
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#endif
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//
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//
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// Release PB4 (Y_ENABLE_PIN) from JTAG NRST role
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// Release JTAG pins but keep SWD enabled
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// - PA15 (JTDI / USART2 RX)
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// - PB3 (JTDO / E0_DIR)
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// - PB4 (NJTRST / E0_STEP)
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//
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//
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//#define DISABLE_DEBUG
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//#define DISABLE_DEBUG
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//#define DISABLE_JTAG
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#define DISABLE_JTAG
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//
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//
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// EEPROM
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// EEPROM
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@ -46,10 +46,13 @@
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#endif
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#endif
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//
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//
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// Release PB4 (Y_ENABLE_PIN) from JTAG NRST role
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// Release JTAG pins but keep SWD enabled
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// - PA15 (JTDI / E0_DIR_PIN)
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// - PB3 (JTDO / E0_STEP_PIN)
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// - PB4 (NJTRST / E0_ENABLE_PIN)
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//
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//
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//#define DISABLE_DEBUG
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//#define DISABLE_DEBUG
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//#define DISABLE_JTAG
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#define DISABLE_JTAG
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//
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//
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// EEPROM
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// EEPROM
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