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Safer delays for EINSY_RAMBO + RRDFGSC
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@ -53,7 +53,7 @@
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#define CPU_ST7920_DELAY_1 DELAY_NS(0)
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#define CPU_ST7920_DELAY_1 DELAY_NS(0)
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#define CPU_ST7920_DELAY_2 DELAY_NS(188)
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#define CPU_ST7920_DELAY_2 DELAY_NS(188)
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#define CPU_ST7920_DELAY_3 DELAY_NS(0)
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#define CPU_ST7920_DELAY_3 DELAY_NS(0)
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#elif MB(MINIRAMBO)
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#elif MB(MINIRAMBO) || MB(EINSY_RAMBO)
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#define CPU_ST7920_DELAY_1 DELAY_NS(0)
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#define CPU_ST7920_DELAY_1 DELAY_NS(0)
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#define CPU_ST7920_DELAY_2 DELAY_NS(250)
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#define CPU_ST7920_DELAY_2 DELAY_NS(250)
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#define CPU_ST7920_DELAY_3 DELAY_NS(0)
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#define CPU_ST7920_DELAY_3 DELAY_NS(0)
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