mirror of
https://github.com/MarlinFirmware/Marlin.git
synced 2024-11-26 13:25:54 +00:00
Minor HAL cleanup
This commit is contained in:
Scott Lahteine
parent
40fdf8f087
commit
bc7720c0cd
@ -147,4 +147,4 @@ uint8_t u8g_com_HAL_DUE_shared_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_va
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#endif // HAS_GRAPHICAL_LCD
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#endif //__SAM3X8E__
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#endif // __SAM3X8E__
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@ -57,4 +57,4 @@ void SoftwareSerial::stopListening() {
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listening = false;
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}
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#endif //__STM32F1__
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#endif // __STM32F1__
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@ -72,7 +72,7 @@ static SPISettings spiConfig;
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*/
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void spiBegin() {
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#if !defined(SS_PIN) || SS_PIN < 0
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#error SS_PIN not defined!
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#error "SS_PIN not defined!"
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#endif
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OUT_WRITE(SS_PIN, HIGH);
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@ -44,8 +44,10 @@
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//#undef MOTHERBOARD
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//#define MOTHERBOARD BOARD_TEENSY31_32
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#define IS_32BIT_TEENSY defined(__MK20DX256__)
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#define IS_TEENSY32 defined(__MK20DX256__)
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#ifdef __MK20DX256__
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#define IS_32BIT_TEENSY 1
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#define IS_TEENSY32 1
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#endif
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#define NUM_SERIAL 1
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@ -45,9 +45,14 @@
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// Defines
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// ------------------------
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#define IS_32BIT_TEENSY (defined(__MK64FX512__) || defined(__MK66FX1M0__))
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#define IS_TEENSY35 defined(__MK64FX512__)
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#define IS_TEENSY36 defined(__MK66FX1M0__)
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#ifdef __MK64FX512__
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#define IS_32BIT_TEENSY 1
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#define IS_TEENSY35 1
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#endif
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#ifdef __MK66FX1M0__
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#define IS_32BIT_TEENSY 1
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#define IS_TEENSY36 1
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#endif
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#define NUM_SERIAL 1
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@ -31,7 +31,7 @@ static SPISettings spiConfig;
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void spiBegin() {
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#if !PIN_EXISTS(SS)
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#error SS_PIN not defined!
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#error "SS_PIN not defined!"
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#endif
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OUT_WRITE(SS_PIN, HIGH);
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SET_OUTPUT(SCK_PIN);
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@ -20,124 +20,126 @@
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/* Validate address */
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#ifdef ARDUINO_ARCH_SAM
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// For DUE, valid address ranges are
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// SRAM (0x20070000 - 0x20088000) (96kb)
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// FLASH (0x00080000 - 0x00100000) (512kb)
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//
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#define START_SRAM_ADDR 0x20070000
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#define END_SRAM_ADDR 0x20088000
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#define START_FLASH_ADDR 0x00080000
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#define END_FLASH_ADDR 0x00100000
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#endif
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#ifdef TARGET_LPC1768
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// For LPC1769:
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// SRAM (0x10000000 - 0x10008000) (32kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x10000000
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#define END_SRAM_ADDR 0x10008000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#endif
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// For DUE, valid address ranges are
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// SRAM (0x20070000 - 0x20088000) (96kb)
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// FLASH (0x00080000 - 0x00100000) (512kb)
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//
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#define START_SRAM_ADDR 0x20070000
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#define END_SRAM_ADDR 0x20088000
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#define START_FLASH_ADDR 0x00080000
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#define END_FLASH_ADDR 0x00100000
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#if 0
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// For STM32F103CBT6
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// SRAM (0x20000000 - 0x20005000) (20kb)
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// FLASH (0x00000000 - 0x00020000) (128kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20005000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00020000
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#endif
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#elif defined(TARGET_LPC1768)
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#if defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx)
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// For STM32F103ZET6/STM32F103VET6/STM32F0xx
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// SRAM (0x20000000 - 0x20010000) (64kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20010000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#endif
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// For LPC1769:
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// SRAM (0x10000000 - 0x10008000) (32kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x10000000
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#define END_SRAM_ADDR 0x10008000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#if defined(STM32F4) || defined(STM32F4xx)
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// For STM32F407VET
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// SRAM (0x20000000 - 0x20030000) (192kb)
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// FLASH (0x08000000 - 0x08080000) (512kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20030000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08080000
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#endif
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#elif 0
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#if MB(THE_BORG)
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// For STM32F765 in BORG
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// SRAM (0x20000000 - 0x20080000) (512kb)
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// FLASH (0x08000000 - 0x08100000) (1024kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20080000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08100000
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#endif
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// For STM32F103CBT6
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// SRAM (0x20000000 - 0x20005000) (20kb)
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// FLASH (0x00000000 - 0x00020000) (128kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20005000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00020000
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#if MB(REMRAM_V1)
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// For STM32F765VI in RemRam v1
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// SRAM (0x20000000 - 0x20080000) (512kb)
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// FLASH (0x08000000 - 0x08200000) (2048kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20080000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08200000
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#endif
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#elif defined(__STM32F1__) || defined(STM32F1xx) || defined(STM32F0xx)
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#ifdef __MK20DX256__
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// For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
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// SRAM (0x1FFF8000 - 0x20008000) (64kb)
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// FLASH (0x00000000 - 0x00040000) (256kb)
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//
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#define START_SRAM_ADDR 0x1FFF8000
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#define END_SRAM_ADDR 0x20008000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00040000
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#endif
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// For STM32F103ZET6/STM32F103VET6/STM32F0xx
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// SRAM (0x20000000 - 0x20010000) (64kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20010000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#ifdef __MK64FX512__
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// For MK64FX512 in TEENSY 3.5
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// SRAM (0x1FFF0000 - 0x20020000) (192kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x1FFF0000
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#define END_SRAM_ADDR 0x20020000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#endif
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#elif defined(STM32F4) || defined(STM32F4xx)
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#ifdef __MK66FX1M0__
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// For MK66FX1M0 in TEENSY 3.6
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// SRAM (0x1FFF0000 - 0x20030000) (256kb)
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// FLASH (0x00000000 - 0x00140000) (1.25Mb)
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//
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#define START_SRAM_ADDR 0x1FFF0000
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#define END_SRAM_ADDR 0x20030000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00140000
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#endif
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// For STM32F407VET
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// SRAM (0x20000000 - 0x20030000) (192kb)
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// FLASH (0x08000000 - 0x08080000) (512kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20030000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08080000
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#elif MB(THE_BORG)
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// For STM32F765 in BORG
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// SRAM (0x20000000 - 0x20080000) (512kb)
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// FLASH (0x08000000 - 0x08100000) (1024kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20080000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08100000
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#elif MB(REMRAM_V1)
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// For STM32F765VI in RemRam v1
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// SRAM (0x20000000 - 0x20080000) (512kb)
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// FLASH (0x08000000 - 0x08200000) (2048kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20080000
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#define START_FLASH_ADDR 0x08000000
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#define END_FLASH_ADDR 0x08200000
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#elif defined(__MK20DX256__)
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// For MK20DX256 in TEENSY 3.1 or TEENSY 3.2
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// SRAM (0x1FFF8000 - 0x20008000) (64kb)
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// FLASH (0x00000000 - 0x00040000) (256kb)
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//
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#define START_SRAM_ADDR 0x1FFF8000
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#define END_SRAM_ADDR 0x20008000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00040000
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#elif defined(__MK64FX512__)
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// For MK64FX512 in TEENSY 3.5
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// SRAM (0x1FFF0000 - 0x20020000) (192kb)
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// FLASH (0x00000000 - 0x00080000) (512kb)
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//
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#define START_SRAM_ADDR 0x1FFF0000
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#define END_SRAM_ADDR 0x20020000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00080000
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#elif defined(__MK66FX1M0__)
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// For MK66FX1M0 in TEENSY 3.6
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// SRAM (0x1FFF0000 - 0x20030000) (256kb)
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// FLASH (0x00000000 - 0x00140000) (1.25Mb)
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//
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#define START_SRAM_ADDR 0x1FFF0000
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#define END_SRAM_ADDR 0x20030000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00140000
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#elif defined(__SAMD51P20A__)
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// For SAMD51x20, valid address ranges are
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// SRAM (0x20000000 - 0x20040000) (256kb)
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// FLASH (0x00000000 - 0x00100000) (1024kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20040000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00100000
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#ifdef __SAMD51P20A__
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// For SAMD51x20, valid address ranges are
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// SRAM (0x20000000 - 0x20040000) (256kb)
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// FLASH (0x00000000 - 0x00100000) (1024kb)
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//
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#define START_SRAM_ADDR 0x20000000
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#define END_SRAM_ADDR 0x20040000
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#define START_FLASH_ADDR 0x00000000
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#define END_FLASH_ADDR 0x00100000
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#endif
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static bool validate_addr(uint32_t addr) {
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@ -177,4 +179,4 @@ bool UnwReadB(const uint32_t a, uint8_t *v) {
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return true;
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}
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#endif
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#endif // __arm__ || __thumb__
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