From cd977c70ca7c4a292b1adb75ad7a6222b7c7a190 Mon Sep 17 00:00:00 2001
From: Victor Oliveira <rhapsodyv@gmail.com>
Date: Fri, 7 Aug 2020 03:55:15 -0300
Subject: [PATCH] Fix / optimize FSMC init (#18941)
---
.../STM32F1/dogm/u8g_com_stm32duino_fsmc.cpp | 18 +++++++-----------
Marlin/src/lcd/extui/lib/mks_ui/tft_fsmc.cpp | 18 +++++++-----------
2 files changed, 14 insertions(+), 22 deletions(-)
diff --git a/Marlin/src/HAL/STM32F1/dogm/u8g_com_stm32duino_fsmc.cpp b/Marlin/src/HAL/STM32F1/dogm/u8g_com_stm32duino_fsmc.cpp
index 0f3887d29af..445e53b67f5 100644
--- a/Marlin/src/HAL/STM32F1/dogm/u8g_com_stm32duino_fsmc.cpp
+++ b/Marlin/src/HAL/STM32F1/dogm/u8g_com_stm32duino_fsmc.cpp
@@ -171,16 +171,17 @@ LCD_CONTROLLER_TypeDef *LCD;
void LCD_IO_Init(uint8_t cs, uint8_t rs) {
uint32_t controllerAddress;
+ struct fsmc_nor_psram_reg_map* fsmcPsramRegion;
if (fsmcInit) return;
fsmcInit = 1;
switch (cs) {
- case FSMC_CS_NE1: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION1; break;
+ case FSMC_CS_NE1: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION1; fsmcPsramRegion = FSMC_NOR_PSRAM1_BASE; break;
#if ENABLED(STM32_XL_DENSITY)
- case FSMC_CS_NE2: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION2; break;
- case FSMC_CS_NE3: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION3; break;
- case FSMC_CS_NE4: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION4; break;
+ case FSMC_CS_NE2: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION2; fsmcPsramRegion = FSMC_NOR_PSRAM2_BASE; break;
+ case FSMC_CS_NE3: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION3; fsmcPsramRegion = FSMC_NOR_PSRAM3_BASE; break;
+ case FSMC_CS_NE4: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION4; fsmcPsramRegion = FSMC_NOR_PSRAM4_BASE; break;
#endif
default: return;
}
@@ -246,13 +247,8 @@ void LCD_IO_Init(uint8_t cs, uint8_t rs) {
gpio_set_mode(PIN_MAP[cs].gpio_device, PIN_MAP[cs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_CS_NEx
gpio_set_mode(PIN_MAP[rs].gpio_device, PIN_MAP[rs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_RS_Ax
- #if ENABLED(STM32_XL_DENSITY)
- FSMC_NOR_PSRAM4_BASE->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
- FSMC_NOR_PSRAM4_BASE->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
- #else // PSRAM1 for STM32F103V (high density)
- FSMC_NOR_PSRAM1_BASE->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
- FSMC_NOR_PSRAM1_BASE->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
- #endif
+ fsmcPsramRegion->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
+ fsmcPsramRegion->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
afio_remap(AFIO_REMAP_FSMC_NADV);
diff --git a/Marlin/src/lcd/extui/lib/mks_ui/tft_fsmc.cpp b/Marlin/src/lcd/extui/lib/mks_ui/tft_fsmc.cpp
index a039cbe0cb1..a257d03489c 100644
--- a/Marlin/src/lcd/extui/lib/mks_ui/tft_fsmc.cpp
+++ b/Marlin/src/lcd/extui/lib/mks_ui/tft_fsmc.cpp
@@ -104,16 +104,17 @@
void LCD_IO_Init(uint8_t cs, uint8_t rs) {
uint32_t controllerAddress;
+ struct fsmc_nor_psram_reg_map* fsmcPsramRegion;
if (fsmcInit) return;
fsmcInit = 1;
switch (cs) {
- case FSMC_CS_NE1: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION1; break;
+ case FSMC_CS_NE1: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION1; fsmcPsramRegion = FSMC_NOR_PSRAM1_BASE; break;
#if ENABLED(STM32_XL_DENSITY)
- case FSMC_CS_NE2: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION2; break;
- case FSMC_CS_NE3: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION3; break;
- case FSMC_CS_NE4: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION4; break;
+ case FSMC_CS_NE2: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION2; fsmcPsramRegion = FSMC_NOR_PSRAM2_BASE; break;
+ case FSMC_CS_NE3: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION3; fsmcPsramRegion = FSMC_NOR_PSRAM3_BASE; break;
+ case FSMC_CS_NE4: controllerAddress = (uint32_t)FSMC_NOR_PSRAM_REGION4; fsmcPsramRegion = FSMC_NOR_PSRAM4_BASE; break;
#endif
default: return;
}
@@ -179,13 +180,8 @@
gpio_set_mode(PIN_MAP[cs].gpio_device, PIN_MAP[cs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_CS_NEx
gpio_set_mode(PIN_MAP[rs].gpio_device, PIN_MAP[rs].gpio_bit, GPIO_AF_OUTPUT_PP); //FSMC_RS_Ax
- #if ENABLED(STM32_XL_DENSITY)
- FSMC_NOR_PSRAM4_BASE->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
- FSMC_NOR_PSRAM4_BASE->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
- #else // PSRAM1 for STM32F103V (high density)
- FSMC_NOR_PSRAM1_BASE->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
- FSMC_NOR_PSRAM1_BASE->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
- #endif
+ fsmcPsramRegion->BCR = FSMC_BCR_WREN | FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_MBKEN;
+ fsmcPsramRegion->BTR = (FSMC_DATA_SETUP_TIME << 8) | FSMC_ADDRESS_SETUP_TIME;
afio_remap(AFIO_REMAP_FSMC_NADV);