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Add macros for ST7565 commands
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Scott Lahteine
parent
3b06a8e917
commit
d32beafd21
@ -122,10 +122,26 @@
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#define U8G_DELAY() u8g_10MicroDelay()
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#endif
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#define ST7565_CS() { WRITE(ST7565_CS_PIN,1); U8G_DELAY(); }
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#define ST7565_NCS() { WRITE(ST7565_CS_PIN,0); }
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#define ST7565_A0() { WRITE(ST7565_A0_PIN,1); U8G_DELAY(); }
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#define ST7565_NA0() { WRITE(ST7565_A0_PIN,0); }
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#define ST7565_CS() do{ WRITE(ST7565_CS_PIN, HIGH); U8G_DELAY(); }while(0)
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#define ST7565_NCS() WRITE(ST7565_CS_PIN, LOW)
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#define ST7565_A0() do{ WRITE(ST7565_A0_PIN, HIGH); U8G_DELAY(); }while(0)
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#define ST7565_NA0() WRITE(ST7565_A0_PIN, LOW)
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#define ST7565_ADC_REVERSE(N) ST7565_WRITE_BYTE(0xA0 | ((N) & 0x1))
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#define ST7565_BIAS_MODE(N) ST7565_WRITE_BYTE(0xA2 | ((N) & 0x1))
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#define ST7565_ALL_PIX(N) ST7565_WRITE_BYTE(0xA4 | ((N) & 0x1))
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#define ST7565_INVERTED(N) ST7565_WRITE_BYTE(0xA6 | ((N) & 0x1))
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#define ST7565_ON(N) ST7565_WRITE_BYTE(0xAE | ((N) & 0x1))
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#define ST7565_OUT_MODE(N) ST7565_WRITE_BYTE(0xC0 | ((N) & 0x1) << 3)
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#define ST7565_POWER_CONTROL(N) ST7565_WRITE_BYTE(0x28 | (N))
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#define ST7565_V0_RATIO(N) ST7565_WRITE_BYTE(0x20 | ((N) & 0x7))
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#define ST7565_CONTRAST(N) do{ ST7565_WRITE_BYTE(0x81); ST7565_WRITE_BYTE(N); }while(0)
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#define ST7565_COLUMN_ADR(N) do{ ST7565_WRITE_BYTE(0x10 | ((N) >> 4) & 0xF); ST7565_WRITE_BYTE(0x00 | ((N) & 0xF)); }while(0)
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#define ST7565_PAGE_ADR(N) ST7565_WRITE_BYTE(0xB0 | (N))
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#define ST7565_START_LINE(N) ST7565_WRITE_BYTE(0x40 | (N))
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#define ST7565_SLEEP_MODE() ST7565_WRITE_BYTE(0xAC)
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#define ST7565_NOOP() ST7565_WRITE_BYTE(0xE3)
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uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
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switch (msg) {
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@ -144,96 +160,90 @@ uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg
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OUT_WRITE(ST7565_A0_PIN, LOW);
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ST7565_CS(); /* disable chip */
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ST7565_NA0(); /* instruction mode */
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ST7565_NCS(); /* enable chip */
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ST7565_CS(); // chip select off
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ST7565_NA0(); // instruction mode
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ST7565_NCS(); // chip select
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ST7565_WRITE_BYTE(0x0A2); /* 0x0A2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
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ST7565_WRITE_BYTE(0x0A0); /* Normal ADC Select (according to Displaytech 64128N datasheet) */
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ST7565_BIAS_MODE(0); // 0xA2: LCD bias 1/9 (according to Displaytech 64128N datasheet)
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ST7565_ADC_REVERSE(0); // Normal (not flipped) ADC Select (according to Displaytech 64128N datasheet)
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ST7565_WRITE_BYTE(0x0C8); /* common output mode: set scan direction normal operation/SHL Select; 0x0C0 --> SHL = 0; normal; 0x0C8 --> SHL = 1 */
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ST7565_WRITE_BYTE(0x040); /* Display start line for Displaytech 64128N */
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ST7565_OUT_MODE(1); // common output mode: set scan direction normal operation/SHL Select; 0x0C0 --> SHL = 0; normal; 0x0C8 --> SHL = 1
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ST7565_START_LINE(0); // Display start line for Displaytech 64128N
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ST7565_WRITE_BYTE(0x028 | 0x04); /* power control: turn on voltage converter */
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//U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
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//ST7565_POWER_CONTROL(0x4); // power control: turn on Booster
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//U8G_ESC_DLY(50); // delay 50 ms - hangs after a reset if used
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ST7565_WRITE_BYTE(0x028 | 0x06); /* power control: turn on voltage regulator */
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//U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
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//ST7565_POWER_CONTROL(0x6); // power control: turn on Booster, Voltage Regulator
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//U8G_ESC_DLY(50); // delay 50 ms - hangs after a reset if used
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ST7565_WRITE_BYTE(0x028 | 0x07); /* power control: turn on voltage follower */
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//U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
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ST7565_POWER_CONTROL(0x7); // power control: turn on Booster, Voltage Regulator, Voltage Follower
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//U8G_ESC_DLY(50); // delay 50 ms - hangs after a reset if used
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ST7565_WRITE_BYTE(0x010); /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
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ST7565_V0_RATIO(0); // Set V0 Voltage Resistor ratio. Setting for controlling brightness of Displaytech 64128N
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ST7565_WRITE_BYTE(0x0A6); /* display normal, bit val 0: LCD pixel off. */
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ST7565_INVERTED(0); // display normal, bit val 0: LCD pixel off.
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ST7565_WRITE_BYTE(0x081); /* set contrast */
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ST7565_WRITE_BYTE(0x01E); /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
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ST7565_CONTRAST(0x1E); // Contrast value. Setting for controlling contrast of Displaytech 64128N
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ST7565_WRITE_BYTE(0x0AF); /* display on */
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ST7565_ON(1); // display on
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U8G_ESC_DLY(100); /* delay 100 ms */
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ST7565_WRITE_BYTE(0x0A5); /* display all points; ST7565 */
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U8G_ESC_DLY(100); /* delay 100 ms */
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U8G_ESC_DLY(100); /* delay 100 ms */
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ST7565_WRITE_BYTE(0x0A4); /* normal display */
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ST7565_CS(); /* disable chip */
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} /* end of sequence */
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U8G_ESC_DLY(100); // delay 100 ms
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ST7565_ALL_PIX(1); // display all points; ST7565
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U8G_ESC_DLY(100); // delay 100 ms
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U8G_ESC_DLY(100); // delay 100 ms
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ST7565_ALL_PIX(0); // normal display
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ST7565_CS(); // chip select off
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} // end of sequence
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break;
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case U8G_DEV_MSG_STOP: break;
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case U8G_DEV_MSG_PAGE_NEXT: {
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u8g_pb_t *pb = (u8g_pb_t*)(dev->dev_mem);
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ST7565_CS(); /* disable chip */
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ST7565_NA0(); /* instruction mode */
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ST7565_NCS(); /* enable chip */
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ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */
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ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
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/* end of sequence */
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ST7565_WRITE_BYTE(0x0B0 | (2*pb->p.page));; /* select current page (ST7565R) */
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ST7565_A0(); /* data mode */
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ST7565_CS(); // chip select off
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ST7565_NA0(); // instruction mode
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ST7565_NCS(); // chip select
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ST7565_COLUMN_ADR(0x00); // high 4 bits to 0, low 4 bits to 0. Changed for DisplayTech 64128N
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// end of sequence
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ST7565_PAGE_ADR(2 * pb->p.page); // select current page (ST7565R)
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ST7565_A0(); // data mode
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ST7560_WriteSequence((uint8_t)pb->width, (uint8_t*)pb->buf);
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ST7565_CS(); /* disable chip */
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ST7565_NA0(); /* instruction mode */
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ST7565_NCS(); /* enable chip */
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ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */
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ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
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/* end of sequence */
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ST7565_WRITE_BYTE(0x0B0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
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ST7565_A0(); /* data mode */
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ST7565_CS(); // chip select off
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ST7565_NA0(); // instruction mode
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ST7565_NCS(); // chip select
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ST7565_COLUMN_ADR(0x00); // high 4 bits to 0, low 4 bits to 0
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// end of sequence
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ST7565_PAGE_ADR(2 * pb->p.page + 1); // select current page (ST7565R)
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ST7565_A0(); // data mode
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ST7560_WriteSequence((uint8_t)pb->width, (uint8_t*)(pb->buf) + pb->width);
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ST7565_CS(); /* disable chip */
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ST7565_CS(); // chip select off
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}
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break;
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case U8G_DEV_MSG_CONTRAST:
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ST7565_NCS();
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ST7565_NA0(); /* instruction mode */
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ST7565_WRITE_BYTE(0x081);
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ST7565_WRITE_BYTE((*(uint8_t *)arg) >> 2);
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ST7565_CS(); /* disable chip */
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ST7565_NA0(); // instruction mode
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ST7565_CONTRAST((*(uint8_t*)arg) >> 2);
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ST7565_CS(); // chip select off
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return 1;
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case U8G_DEV_MSG_SLEEP_ON:
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ST7565_NA0(); /* instruction mode */
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ST7565_NCS(); /* enable chip */
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ST7565_WRITE_BYTE(0x0AC); /* static indicator off */
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ST7565_WRITE_BYTE(0x000); /* indicator register set (not sure if this is required) */
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ST7565_WRITE_BYTE(0x0AE); /* display off */
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ST7565_WRITE_BYTE(0x0A5); /* all points on */
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ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */
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/* end of sequence */
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ST7565_NA0(); // instruction mode
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ST7565_NCS(); // chip select
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ST7565_SLEEP_MODE(); // static indicator off
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//ST7565_WRITE_BYTE(0x00); // indicator register set (not sure if this is required)
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ST7565_ON(0); // display off
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ST7565_ALL_PIX(1); // all points on
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ST7565_CS(); // chip select off
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return 1;
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case U8G_DEV_MSG_SLEEP_OFF:
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ST7565_NA0(); /* instruction mode */
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ST7565_NCS(); /* enable chip */
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ST7565_WRITE_BYTE(0x0A4); /* all points off */
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ST7565_WRITE_BYTE(0x0AF); /* display on */
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U8G_ESC_DLY(50); /* delay 50 ms */
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ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */
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/* end of sequence */
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ST7565_NA0(); // instruction mode
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ST7565_NCS(); // chip select
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ST7565_ALL_PIX(0); // all points off
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ST7565_ON(1); // display on
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U8G_ESC_DLY(50); // delay 50 ms
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ST7565_CS(); // chip select off
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return 1;
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}
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return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
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