10 commits

Author	SHA1	Message	Date
Scott Lahteine	93cd66ac11	Tweaky change from (C) to (c)	2019-06-27 23:58:16 -05:00
Scott Lahteine	26de051e92	HAL SPI pin init cleanup	2019-06-14 20:17:25 -05:00
Scott Lahteine	3a1b6fe8c1	Coding standards	2019-02-19 14:58:39 -06:00
Scott Lahteine	0feeef2604	Update copyright in headers	2019-02-12 15:30:11 -06:00
etagle	0566badcef	Add memory barrier, optimal interrupt on-off ... Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)	2018-05-20 02:39:34 -05:00
Chris Pepper	cc6d41e1d3	Use a macro for HAL header redirection (#10380)	2018-04-12 20:25:08 -05:00
Scott Lahteine	ac368f2788	Add STEPPER_ISR_ENABLED() to HALs ... Some also get a `HAL_timer_interrupt_enabled` function.	2018-01-14 21:07:10 -06:00
Scott Lahteine	c2b1d51f16	HAL whitespace and style cleanup	2017-09-27 10:55:36 -05:00
Scott Lahteine	2af62a5d8d	Apply spacing, const to some HAL code	2017-08-31 18:33:07 -05:00
teemuatlut	f3e562e46e	HAL for 32-bit Teensy (3.5, 3.6) architecture	2017-08-31 18:15:07 -05:00