mirror of
https://github.com/MarlinFirmware/Marlin.git
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f991bf23b2
Added the optiboot bootloader, uses only 512kB of FLASH Includes .hex file is for 20MHz µC Clock and serial speed of 57k6
848 lines
33 KiB
C
848 lines
33 KiB
C
/* Modified to use out for SPM access
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** Peter Knight, Optiboot project http://optiboot.googlecode.com
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**
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** Todo: Tidy up
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**
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** "_short" routines execute 1 cycle faster and use 1 less word of flash
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** by using "out" instruction instead of "sts".
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**
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** Additional elpm variants that trust the value of RAMPZ
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*/
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/* Copyright (c) 2002, 2003, 2004, 2005, 2006, 2007 Eric B. Weddington
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id: boot.h,v 1.27.2.3 2008/09/30 13:58:48 arcanum Exp $ */
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#ifndef _AVR_BOOT_H_
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#define _AVR_BOOT_H_ 1
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/** \file */
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/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
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\code
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#include <avr/io.h>
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#include <avr/boot.h>
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\endcode
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The macros in this module provide a C language interface to the
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bootloader support functionality of certain AVR processors. These
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macros are designed to work with all sizes of flash memory.
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Global interrupts are not automatically disabled for these macros. It
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is left up to the programmer to do this. See the code example below.
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Also see the processor datasheet for caveats on having global interrupts
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enabled during writing of the Flash.
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\note Not all AVR processors provide bootloader support. See your
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processor datasheet to see if it provides bootloader support.
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\todo From email with Marek: On smaller devices (all except ATmega64/128),
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__SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
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instructions - since the boot loader has a limited size, this could be an
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important optimization.
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\par API Usage Example
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The following code shows typical usage of the boot API.
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\code
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#include <inttypes.h>
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#include <avr/interrupt.h>
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#include <avr/pgmspace.h>
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void boot_program_page (uint32_t page, uint8_t *buf)
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{
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uint16_t i;
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uint8_t sreg;
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// Disable interrupts.
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sreg = SREG;
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cli();
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eeprom_busy_wait ();
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boot_page_erase (page);
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boot_spm_busy_wait (); // Wait until the memory is erased.
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for (i=0; i<SPM_PAGESIZE; i+=2)
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{
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// Set up little-endian word.
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uint16_t w = *buf++;
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w += (*buf++) << 8;
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boot_page_fill (page + i, w);
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}
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boot_page_write (page); // Store buffer in flash page.
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boot_spm_busy_wait(); // Wait until the memory is written.
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// Reenable RWW-section again. We need this if we want to jump back
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// to the application after bootloading.
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boot_rww_enable ();
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// Re-enable interrupts (if they were ever enabled).
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SREG = sreg;
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}\endcode */
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#include <avr/eeprom.h>
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#include <avr/io.h>
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#include <inttypes.h>
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#include <limits.h>
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/* Check for SPM Control Register in processor. */
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#if defined (SPMCSR)
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# define __SPM_REG SPMCSR
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#elif defined (SPMCR)
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# define __SPM_REG SPMCR
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#else
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# error AVR processor does not provide bootloader support!
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#endif
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/* Check for SPM Enable bit. */
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#if defined(SPMEN)
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# define __SPM_ENABLE SPMEN
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#elif defined(SELFPRGEN)
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# define __SPM_ENABLE SELFPRGEN
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#else
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# error Cannot find SPM Enable bit definition!
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#endif
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/** \ingroup avr_boot
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\def BOOTLOADER_SECTION
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Used to declare a function or variable to be placed into a
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new section called .bootloader. This section and its contents
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can then be relocated to any address (such as the bootloader
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NRWW area) at link-time. */
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#define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
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/* Create common bit definitions. */
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#ifdef ASB
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#define __COMMON_ASB ASB
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#else
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#define __COMMON_ASB RWWSB
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#endif
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#ifdef ASRE
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#define __COMMON_ASRE ASRE
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#else
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#define __COMMON_ASRE RWWSRE
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#endif
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/* Define the bit positions of the Boot Lock Bits. */
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#define BLB12 5
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#define BLB11 4
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#define BLB02 3
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#define BLB01 2
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/** \ingroup avr_boot
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\def boot_spm_interrupt_enable()
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Enable the SPM interrupt. */
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#define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
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/** \ingroup avr_boot
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\def boot_spm_interrupt_disable()
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Disable the SPM interrupt. */
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#define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
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/** \ingroup avr_boot
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\def boot_is_spm_interrupt()
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Check if the SPM interrupt is enabled. */
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#define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
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/** \ingroup avr_boot
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\def boot_rww_busy()
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Check if the RWW section is busy. */
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#define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
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/** \ingroup avr_boot
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\def boot_spm_busy()
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Check if the SPM instruction is busy. */
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#define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
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/** \ingroup avr_boot
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\def boot_spm_busy_wait()
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Wait while the SPM instruction is busy. */
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#define boot_spm_busy_wait() do{}while(boot_spm_busy())
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#define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
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#define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
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#define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
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#define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
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#define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
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#define __boot_page_fill_short(address, data) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r0, %3\n\t" \
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"out %0, %1\n\t" \
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"spm\n\t" \
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"clr r1\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_FILL), \
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"z" ((uint16_t)address), \
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"r" ((uint16_t)data) \
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: "r0" \
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); \
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}))
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#define __boot_page_fill_normal(address, data) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r0, %3\n\t" \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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"clr r1\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_FILL), \
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"z" ((uint16_t)address), \
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"r" ((uint16_t)data) \
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: "r0" \
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); \
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}))
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#define __boot_page_fill_alternate(address, data)\
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r0, %3\n\t" \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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".word 0xffff\n\t" \
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"nop\n\t" \
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"clr r1\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_FILL), \
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"z" ((uint16_t)address), \
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"r" ((uint16_t)data) \
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: "r0" \
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); \
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}))
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#define __boot_page_fill_extended(address, data) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r0, %4\n\t" \
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"movw r30, %A3\n\t" \
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"sts %1, %C3\n\t" \
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"sts %0, %2\n\t" \
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"spm\n\t" \
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"clr r1\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"i" (_SFR_MEM_ADDR(RAMPZ)), \
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"r" ((uint8_t)__BOOT_PAGE_FILL), \
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"r" ((uint32_t)address), \
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"r" ((uint16_t)data) \
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: "r0", "r30", "r31" \
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); \
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}))
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#define __boot_page_fill_extended_short(address, data) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r0, %4\n\t" \
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"movw r30, %A3\n\t" \
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"out %1, %C3\n\t" \
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"out %0, %2\n\t" \
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"spm\n\t" \
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"clr r1\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"i" (_SFR_IO_ADDR(RAMPZ)), \
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"r" ((uint8_t)__BOOT_PAGE_FILL), \
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"r" ((uint32_t)address), \
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"r" ((uint16_t)data) \
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: "r0", "r30", "r31" \
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); \
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}))
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#define __boot_page_erase_short(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"out %0, %1\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_ERASE), \
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"z" ((uint16_t)address) \
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); \
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}))
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#define __boot_page_erase_normal(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_ERASE), \
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"z" ((uint16_t)address) \
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); \
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}))
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#define __boot_page_erase_alternate(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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".word 0xffff\n\t" \
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"nop\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_ERASE), \
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"z" ((uint16_t)address) \
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); \
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}))
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#define __boot_page_erase_extended(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r30, %A3\n\t" \
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"sts %1, %C3\n\t" \
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"sts %0, %2\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"i" (_SFR_MEM_ADDR(RAMPZ)), \
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"r" ((uint8_t)__BOOT_PAGE_ERASE), \
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"r" ((uint32_t)address) \
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: "r30", "r31" \
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); \
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}))
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#define __boot_page_erase_extended_short(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r30, %A3\n\t" \
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"out %1, %C3\n\t" \
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"out %0, %2\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"i" (_SFR_IO_ADDR(RAMPZ)), \
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"r" ((uint8_t)__BOOT_PAGE_ERASE), \
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"r" ((uint32_t)address) \
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: "r30", "r31" \
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); \
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}))
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#define __boot_page_write_short(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"out %0, %1\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_WRITE), \
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"z" ((uint16_t)address) \
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); \
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}))
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#define __boot_page_write_normal(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_WRITE), \
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"z" ((uint16_t)address) \
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); \
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}))
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#define __boot_page_write_alternate(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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".word 0xffff\n\t" \
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"nop\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_PAGE_WRITE), \
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"z" ((uint16_t)address) \
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); \
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}))
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#define __boot_page_write_extended(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r30, %A3\n\t" \
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"sts %1, %C3\n\t" \
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"sts %0, %2\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"i" (_SFR_MEM_ADDR(RAMPZ)), \
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"r" ((uint8_t)__BOOT_PAGE_WRITE), \
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"r" ((uint32_t)address) \
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: "r30", "r31" \
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); \
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}))
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#define __boot_page_write_extended_short(address) \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"movw r30, %A3\n\t" \
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"out %1, %C3\n\t" \
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"out %0, %2\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"i" (_SFR_IO_ADDR(RAMPZ)), \
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"r" ((uint8_t)__BOOT_PAGE_WRITE), \
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"r" ((uint32_t)address) \
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: "r30", "r31" \
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); \
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}))
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#define __boot_rww_enable_short() \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"out %0, %1\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_IO_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_RWW_ENABLE) \
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); \
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}))
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#define __boot_rww_enable() \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_RWW_ENABLE) \
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); \
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}))
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#define __boot_rww_enable_alternate() \
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(__extension__({ \
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__asm__ __volatile__ \
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( \
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"sts %0, %1\n\t" \
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"spm\n\t" \
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".word 0xffff\n\t" \
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"nop\n\t" \
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: \
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: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
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"r" ((uint8_t)__BOOT_RWW_ENABLE) \
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); \
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}))
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/* From the mega16/mega128 data sheets (maybe others):
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|
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Bits by SPM To set the Boot Loader Lock bits, write the desired data to
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R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
|
|
after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
|
|
that may prevent the Application and Boot Loader section from any
|
|
software update by the MCU.
|
|
|
|
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
|
|
will be programmed if an SPM instruction is executed within four cycles
|
|
after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
|
|
don't care during this operation, but for future compatibility it is
|
|
recommended to load the Z-pointer with $0001 (same as used for reading the
|
|
Lock bits). For future compatibility It is also recommended to set bits 7,
|
|
6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
|
|
Lock bits the entire Flash can be read during the operation. */
|
|
|
|
#define __boot_lock_bits_set_short(lock_bits) \
|
|
(__extension__({ \
|
|
uint8_t value = (uint8_t)(~(lock_bits)); \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"ldi r30, 1\n\t" \
|
|
"ldi r31, 0\n\t" \
|
|
"mov r0, %2\n\t" \
|
|
"out %0, %1\n\t" \
|
|
"spm\n\t" \
|
|
: \
|
|
: "i" (_SFR_IO_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
|
"r" (value) \
|
|
: "r0", "r30", "r31" \
|
|
); \
|
|
}))
|
|
|
|
#define __boot_lock_bits_set(lock_bits) \
|
|
(__extension__({ \
|
|
uint8_t value = (uint8_t)(~(lock_bits)); \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"ldi r30, 1\n\t" \
|
|
"ldi r31, 0\n\t" \
|
|
"mov r0, %2\n\t" \
|
|
"sts %0, %1\n\t" \
|
|
"spm\n\t" \
|
|
: \
|
|
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
|
"r" (value) \
|
|
: "r0", "r30", "r31" \
|
|
); \
|
|
}))
|
|
|
|
#define __boot_lock_bits_set_alternate(lock_bits) \
|
|
(__extension__({ \
|
|
uint8_t value = (uint8_t)(~(lock_bits)); \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"ldi r30, 1\n\t" \
|
|
"ldi r31, 0\n\t" \
|
|
"mov r0, %2\n\t" \
|
|
"sts %0, %1\n\t" \
|
|
"spm\n\t" \
|
|
".word 0xffff\n\t" \
|
|
"nop\n\t" \
|
|
: \
|
|
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
|
"r" (value) \
|
|
: "r0", "r30", "r31" \
|
|
); \
|
|
}))
|
|
|
|
/*
|
|
Reading lock and fuse bits:
|
|
|
|
Similarly to writing the lock bits above, set BLBSET and SPMEN (or
|
|
SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
|
|
LPM instruction.
|
|
|
|
Z address: contents:
|
|
0x0000 low fuse bits
|
|
0x0001 lock bits
|
|
0x0002 extended fuse bits
|
|
0x0003 high fuse bits
|
|
|
|
Sounds confusing, doesn't it?
|
|
|
|
Unlike the macros in pgmspace.h, no need to care for non-enhanced
|
|
cores here as these old cores do not provide SPM support anyway.
|
|
*/
|
|
|
|
/** \ingroup avr_boot
|
|
\def GET_LOW_FUSE_BITS
|
|
address to read the low fuse bits, using boot_lock_fuse_bits_get
|
|
*/
|
|
#define GET_LOW_FUSE_BITS (0x0000)
|
|
/** \ingroup avr_boot
|
|
\def GET_LOCK_BITS
|
|
address to read the lock bits, using boot_lock_fuse_bits_get
|
|
*/
|
|
#define GET_LOCK_BITS (0x0001)
|
|
/** \ingroup avr_boot
|
|
\def GET_EXTENDED_FUSE_BITS
|
|
address to read the extended fuse bits, using boot_lock_fuse_bits_get
|
|
*/
|
|
#define GET_EXTENDED_FUSE_BITS (0x0002)
|
|
/** \ingroup avr_boot
|
|
\def GET_HIGH_FUSE_BITS
|
|
address to read the high fuse bits, using boot_lock_fuse_bits_get
|
|
*/
|
|
#define GET_HIGH_FUSE_BITS (0x0003)
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_lock_fuse_bits_get(address)
|
|
|
|
Read the lock or fuse bits at \c address.
|
|
|
|
Parameter \c address can be any of GET_LOW_FUSE_BITS,
|
|
GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
|
|
|
|
\note The lock and fuse bits returned are the physical values,
|
|
i.e. a bit returned as 0 means the corresponding fuse or lock bit
|
|
is programmed.
|
|
*/
|
|
#define boot_lock_fuse_bits_get_short(address) \
|
|
(__extension__({ \
|
|
uint8_t __result; \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"ldi r30, %3\n\t" \
|
|
"ldi r31, 0\n\t" \
|
|
"out %1, %2\n\t" \
|
|
"lpm %0, Z\n\t" \
|
|
: "=r" (__result) \
|
|
: "i" (_SFR_IO_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
|
"M" (address) \
|
|
: "r0", "r30", "r31" \
|
|
); \
|
|
__result; \
|
|
}))
|
|
|
|
#define boot_lock_fuse_bits_get(address) \
|
|
(__extension__({ \
|
|
uint8_t __result; \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"ldi r30, %3\n\t" \
|
|
"ldi r31, 0\n\t" \
|
|
"sts %1, %2\n\t" \
|
|
"lpm %0, Z\n\t" \
|
|
: "=r" (__result) \
|
|
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t)__BOOT_LOCK_BITS_SET), \
|
|
"M" (address) \
|
|
: "r0", "r30", "r31" \
|
|
); \
|
|
__result; \
|
|
}))
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_signature_byte_get(address)
|
|
|
|
Read the Signature Row byte at \c address. For some MCU types,
|
|
this function can also retrieve the factory-stored oscillator
|
|
calibration bytes.
|
|
|
|
Parameter \c address can be 0-0x1f as documented by the datasheet.
|
|
\note The values are MCU type dependent.
|
|
*/
|
|
|
|
#define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
|
|
|
|
#define boot_signature_byte_get_short(addr) \
|
|
(__extension__({ \
|
|
uint16_t __addr16 = (uint16_t)(addr); \
|
|
uint8_t __result; \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"out %1, %2\n\t" \
|
|
"lpm %0, Z" "\n\t" \
|
|
: "=r" (__result) \
|
|
: "i" (_SFR_IO_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t) __BOOT_SIGROW_READ), \
|
|
"z" (__addr16) \
|
|
); \
|
|
__result; \
|
|
}))
|
|
|
|
#define boot_signature_byte_get(addr) \
|
|
(__extension__({ \
|
|
uint16_t __addr16 = (uint16_t)(addr); \
|
|
uint8_t __result; \
|
|
__asm__ __volatile__ \
|
|
( \
|
|
"sts %1, %2\n\t" \
|
|
"lpm %0, Z" "\n\t" \
|
|
: "=r" (__result) \
|
|
: "i" (_SFR_MEM_ADDR(__SPM_REG)), \
|
|
"r" ((uint8_t) __BOOT_SIGROW_READ), \
|
|
"z" (__addr16) \
|
|
); \
|
|
__result; \
|
|
}))
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_page_fill(address, data)
|
|
|
|
Fill the bootloader temporary page buffer for flash
|
|
address with data word.
|
|
|
|
\note The address is a byte address. The data is a word. The AVR
|
|
writes data to the buffer a word at a time, but addresses the buffer
|
|
per byte! So, increment your address by 2 between calls, and send 2
|
|
data bytes in a word format! The LSB of the data is written to the lower
|
|
address; the MSB of the data is written to the higher address.*/
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_page_erase(address)
|
|
|
|
Erase the flash page that contains address.
|
|
|
|
\note address is a byte address in flash, not a word address. */
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_page_write(address)
|
|
|
|
Write the bootloader temporary page buffer
|
|
to flash page that contains address.
|
|
|
|
\note address is a byte address in flash, not a word address. */
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_rww_enable()
|
|
|
|
Enable the Read-While-Write memory section. */
|
|
|
|
/** \ingroup avr_boot
|
|
\def boot_lock_bits_set(lock_bits)
|
|
|
|
Set the bootloader lock bits.
|
|
|
|
\param lock_bits A mask of which Boot Loader Lock Bits to set.
|
|
|
|
\note In this context, a 'set bit' will be written to a zero value.
|
|
Note also that only BLBxx bits can be programmed by this command.
|
|
|
|
For example, to disallow the SPM instruction from writing to the Boot
|
|
Loader memory section of flash, you would use this macro as such:
|
|
|
|
\code
|
|
boot_lock_bits_set (_BV (BLB11));
|
|
\endcode
|
|
|
|
\note Like any lock bits, the Boot Loader Lock Bits, once set,
|
|
cannot be cleared again except by a chip erase which will in turn
|
|
also erase the boot loader itself. */
|
|
|
|
/* Normal versions of the macros use 16-bit addresses.
|
|
Extended versions of the macros use 32-bit addresses.
|
|
Alternate versions of the macros use 16-bit addresses and require special
|
|
instruction sequences after LPM.
|
|
|
|
FLASHEND is defined in the ioXXXX.h file.
|
|
USHRT_MAX is defined in <limits.h>. */
|
|
|
|
#if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
|
|
|| defined(__AVR_ATmega323__)
|
|
|
|
/* Alternate: ATmega161/163/323 and 16 bit address */
|
|
#define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
|
|
#define boot_page_erase(address) __boot_page_erase_alternate(address)
|
|
#define boot_page_write(address) __boot_page_write_alternate(address)
|
|
#define boot_rww_enable() __boot_rww_enable_alternate()
|
|
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
|
|
|
|
#elif (FLASHEND > USHRT_MAX)
|
|
|
|
/* Extended: >16 bit address */
|
|
#define boot_page_fill(address, data) __boot_page_fill_extended_short(address, data)
|
|
#define boot_page_erase(address) __boot_page_erase_extended_short(address)
|
|
#define boot_page_write(address) __boot_page_write_extended_short(address)
|
|
#define boot_rww_enable() __boot_rww_enable_short()
|
|
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_short(lock_bits)
|
|
|
|
#else
|
|
|
|
/* Normal: 16 bit address */
|
|
#define boot_page_fill(address, data) __boot_page_fill_short(address, data)
|
|
#define boot_page_erase(address) __boot_page_erase_short(address)
|
|
#define boot_page_write(address) __boot_page_write_short(address)
|
|
#define boot_rww_enable() __boot_rww_enable_short()
|
|
#define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_short(lock_bits)
|
|
|
|
#endif
|
|
|
|
/** \ingroup avr_boot
|
|
|
|
Same as boot_page_fill() except it waits for eeprom and spm operations to
|
|
complete before filling the page. */
|
|
|
|
#define boot_page_fill_safe(address, data) \
|
|
do { \
|
|
boot_spm_busy_wait(); \
|
|
eeprom_busy_wait(); \
|
|
boot_page_fill(address, data); \
|
|
} while (0)
|
|
|
|
/** \ingroup avr_boot
|
|
|
|
Same as boot_page_erase() except it waits for eeprom and spm operations to
|
|
complete before erasing the page. */
|
|
|
|
#define boot_page_erase_safe(address) \
|
|
do { \
|
|
boot_spm_busy_wait(); \
|
|
eeprom_busy_wait(); \
|
|
boot_page_erase (address); \
|
|
} while (0)
|
|
|
|
/** \ingroup avr_boot
|
|
|
|
Same as boot_page_write() except it waits for eeprom and spm operations to
|
|
complete before writing the page. */
|
|
|
|
#define boot_page_write_safe(address) \
|
|
do { \
|
|
boot_spm_busy_wait(); \
|
|
eeprom_busy_wait(); \
|
|
boot_page_write (address); \
|
|
} while (0)
|
|
|
|
/** \ingroup avr_boot
|
|
|
|
Same as boot_rww_enable() except waits for eeprom and spm operations to
|
|
complete before enabling the RWW mameory. */
|
|
|
|
#define boot_rww_enable_safe() \
|
|
do { \
|
|
boot_spm_busy_wait(); \
|
|
eeprom_busy_wait(); \
|
|
boot_rww_enable(); \
|
|
} while (0)
|
|
|
|
/** \ingroup avr_boot
|
|
|
|
Same as boot_lock_bits_set() except waits for eeprom and spm operations to
|
|
complete before setting the lock bits. */
|
|
|
|
#define boot_lock_bits_set_safe(lock_bits) \
|
|
do { \
|
|
boot_spm_busy_wait(); \
|
|
eeprom_busy_wait(); \
|
|
boot_lock_bits_set (lock_bits); \
|
|
} while (0)
|
|
|
|
#endif /* _AVR_BOOT_H_ */ |