2021-06-08 13:28:02 +00:00
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#include <stddef.h>
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#include <avr/wdt.h>
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#include <avr/interrupt.h>
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#include "xflash_dump.h"
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2021-06-08 15:17:18 +00:00
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#ifdef XFLASH_DUMP
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2021-06-08 13:28:02 +00:00
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#include "xflash.h"
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2021-06-10 15:02:41 +00:00
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#include "Marlin.h" // for softReset
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2021-06-08 13:28:02 +00:00
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2021-06-11 17:21:51 +00:00
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bool xfdump_check_state(dump_crash_reason* reason)
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2021-06-08 13:28:02 +00:00
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{
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uint32_t magic;
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XFLASH_SPI_ENTER();
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xflash_rd_data(DUMP_OFFSET + offsetof(dump_t, header.magic),
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(uint8_t*)&magic, sizeof(magic));
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2021-06-11 17:21:51 +00:00
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if (magic != DUMP_MAGIC)
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2021-06-08 13:28:02 +00:00
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return false;
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2021-06-11 17:21:51 +00:00
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if (reason)
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{
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xflash_rd_data(DUMP_OFFSET + offsetof(dump_t, header.crash_reason),
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(uint8_t*)reason, sizeof(*reason));
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}
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return true;
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2021-06-08 13:28:02 +00:00
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}
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void xfdump_reset()
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{
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XFLASH_SPI_ENTER();
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xflash_enable_wr();
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xflash_sector_erase(DUMP_OFFSET + offsetof(dump_t, header.magic));
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xflash_wait_busy();
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}
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static void xfdump_erase()
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{
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for(uint32_t addr = DUMP_OFFSET;
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addr < DUMP_OFFSET + DUMP_SIZE;
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addr += 4096)
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{
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xflash_enable_wr();
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xflash_sector_erase(DUMP_OFFSET);
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xflash_wait_busy();
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}
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}
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static void xfdump_dump_core(dump_header_t& hdr, uint32_t addr, uint8_t* buf, uint16_t cnt)
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{
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XFLASH_SPI_ENTER();
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// start by clearing all sectors (we need all of them in any case)
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xfdump_erase();
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// write header
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2021-06-08 17:08:03 +00:00
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static_assert(sizeof(hdr) <= 256, "header is larger than a single page write");
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2021-06-08 13:28:02 +00:00
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xflash_enable_wr();
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xflash_page_program(DUMP_OFFSET, (uint8_t*)&hdr, sizeof(hdr));
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xflash_wait_busy();
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// write data
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2021-06-12 11:16:12 +00:00
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static_assert(sizeof(dump_t::data) <= RAMEND+1, "dump area size insufficient");
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2021-06-08 13:28:02 +00:00
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xflash_multipage_program(addr, buf, cnt);
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}
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2021-06-15 09:47:27 +00:00
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void xfdump_dump(uint16_t sp)
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2021-06-08 13:28:02 +00:00
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{
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dump_header_t buf;
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buf.magic = DUMP_MAGIC;
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buf.regs_present = false;
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2021-06-10 15:35:49 +00:00
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buf.crash_reason = (uint8_t)dump_crash_reason::manual;
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2021-06-15 09:47:27 +00:00
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buf.sp = sp;
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2021-06-08 13:28:02 +00:00
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// write sram only
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xfdump_dump_core(buf, DUMP_OFFSET + offsetof(dump_t, data.sram),
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2021-06-08 15:53:06 +00:00
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(uint8_t*)RAMSTART, RAMSIZE);
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2021-06-08 13:28:02 +00:00
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}
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2021-06-15 09:47:27 +00:00
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void xfdump_full_dump_and_reset(uint16_t sp, dump_crash_reason reason)
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2021-06-08 13:28:02 +00:00
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{
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dump_header_t buf;
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buf.magic = DUMP_MAGIC;
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buf.regs_present = true;
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2021-06-10 15:35:49 +00:00
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buf.crash_reason = (uint8_t)reason;
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2021-06-15 09:47:27 +00:00
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buf.sp = sp;
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2021-06-08 13:28:02 +00:00
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// disable interrupts for a cleaner register dump
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cli();
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2021-06-10 14:24:52 +00:00
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// ensure there's always enough time (with some margin) to dump
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// dump time on w25x20cl: ~150ms
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wdt_enable(WDTO_500MS);
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2021-06-08 13:28:02 +00:00
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// write all addressable ranges (this will trash bidirectional registers)
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2021-06-12 11:16:12 +00:00
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xfdump_dump_core(buf, DUMP_OFFSET + offsetof(dump_t, data), 0, RAMEND+1);
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2021-06-08 13:28:02 +00:00
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2021-06-10 14:24:52 +00:00
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// force a reset even sooner
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2021-06-09 10:59:26 +00:00
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softReset();
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2021-06-08 13:28:02 +00:00
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}
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2021-06-08 15:17:18 +00:00
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#endif
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